The present disclosure relates to semiconductor device manufacturing, and more particularly, to a process for cutting a plurality of gate lines into a plurality of gate stacks.
Field effect transistors (FETs) are widely used in the electronics industry for switching, amplification, filtering and other tasks related to both analog and digital electrical signals. Most common among these are metal oxide semiconductor field effect transistors (MOSFET or MOS), in which a gate structure is energized to create an electric field in an underlying channel region of a semiconductor body, by which electrons are allowed to travel through the channel between a source region and a drain region of the semiconductor body. Complementary MOS (CMOS) devices have become widely used in the semiconductor industry, wherein both n-type and p-type (NMOS and PMOS) transistors are used to fabricate logic and circuitry.
Continuing trends in semiconductor device manufacturing include a reduction in electrical device feature size (scaling), as well as improvements in device performance in terms of device switching speed and power consumption. Recent MOS and CMOS transistor scaling efforts have focused on high k materials having dielectric constants greater than that of silicon oxide (e.g., greater than about 3.9), which can be formed in a thicker layer than scaled silicon oxide, and yet which produce equivalent field effect performance. Another type of CMOS device that is available is one where the gate electrode includes at least a metal gate layer.
In the manufacturing of such devices, a plurality of gate lines including at least a high k gate dielectric and an overlying metal gate are formed on a surface of a semiconductor substrate. Each gate line of the plurality of gate lines can be cut into a plurality of gate stacks that can be used to manufacture field effect transistor devices. In the cutting of gate lines, a stack including at least a photoresist is typically formed on the substrate and atop the plurality of gate lines. At least one pattern is then formed through the stack that exposes an uppermost portion of each gate line. An etching process is used to transfer the at least one pattern to the underlying gate lines. During etching, each underlying gate line is cut into a plurality of gate stacks. After etching, the patterned stack needs to be removed. In conventional processes, a mixture of sulfuric acid and peroxide is used to remove the patterned stack from atop the substrate. Such a mixture not only removes the patterned stack, but can also attack a portion of the metal gate of each gate stack. For example, a mixture of sulfuric acid and peroxide can result in providing gate stacks that have an undercut metal gate. Alternatively, a mixture of sulfuric acid and peroxide can result in material loss of each gate stack if the gate stacks are exposed. Alternatively, the use of a mixture of sulfuric acid and peroxide can result in complete lift off of the gate stacks.
In view of the above, there is a continued for providing an improved method for cutting a plurality of gate lines into gate stacks which avoids the drawbacks associated with prior art methods in which a mixture of sulfuric acid and peroxide are used to remove the pattered stack from the structure.